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NJU6679
PRELIMINARY 128-common x 132-segment BIT MAP LCD DRIVER
GENERAL DESCRIPTION The NJU6679 is a bit map LCD driver to display graphics or characters. It contains 25,344 bits display data RAM, microprocessor interface circuits, instruction decoder, 132-segment and 128-common drivers. The bit image display data is transferred to the display data RAM by serial or 8-bit parallel interface. The NJU6679 displays 128 x 132 dots graphics or 8-character 8-line by 16 x 16 dots character. It oscillates by built-in OSC circuit without any external components. Furthermore, the NJU6679 features Partial Display Function which creates up to 2 blocks of active display area and optimizes duty cycle ratio. This function sets optimum boosted voltage by the combination with both of programmable 6-time voltage booster circuit and 201step electrical variable resistor. As result, it reduces the operating current. The operating voltage from 2.4V to 3.6V and low operating current are useful for small size battery operating items. FEATURES Direct Correspondence between Display Data RAM and LCD Pixel Display Data RAM - 25,344 bits (1.5 times over than display size) 236 LCD Drivers - 128-common and 132-segment Direct Microprocessor Interface for both of 68 and 80 type MPU Serial Interface Partial Display Function (2 blocks of active display area and automatic duty cycle ratio selection) Easy Vertical Scroll by the variable start line address and over size display data RAM Programmable Bias selection ; 1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11,1/12 bias Common Driver Order Assignment by mask option Version C0 to C127(Pin name) C127(Pin NJU6679A Com0 to Com127 Com0 Com127 NJU6679B Com127 to Com0 Com127 Com0 Useful Instruction Set Display Data Read/Write, Display ON/OFF Cont, Inverse Display, Page Address Set, Display Start Line Set, Partial Display, Bias Select, Column Address Set, Status Read, All On/Off, Voltage Booster Circuits Multiple Select(Maximum 6-time), n-Line Inverse, Read Modify Write, Power Saving, ADC Select, etc. Power Supply Circuits for LCD; Programmable Voltage Booster Circuits(6-time Maximum), Regulator, Voltage Follower x 4 Precision Electrical Variable Resistance Low Power Consumption Operating Voltage Package Outline C-MOS Technology --- 2.4V to 3.6V --- COF / TCP / Bumped Chip JUL.10.2000 Ver. 2.1 LCD Driving Voltage --- 6.0V to 18V PACKAGE OUTLINE
NJU6679CL
NJU6679
PAD LOCATION
C45
C46 C47
C1 C0
C63 S0
X
Y
S131 C127
DUMMY19 DUMMY18 DUMMY17 DUMMY16 DUMMY15 DUMMY14 DUMMY13 DUMMY12 VDD V1 V2 V3 V4 V5 VR VDD C1C1 C2C2+ C3C3+ C4C4+ C5C5+ VOUT VSS D7 D6 D5 D4 D3 D2 D1 D0 RD WR A0 CS OSC2 OSC1 T1 T2 VSS RES SEL68 P/S VDD DUMMY11 DUMMY10 DUMMY9 DUMMY8 DUMMY7 DUMMY6 DUMMY5 DUMMY4 DUMMY3 DUMMY2 DUMMY1 1 DUMMY0
+
C111 C110
C109
Chip Center Chip Size Chip Thickness Bump Size Pad pitch Bump Height Bump Material
: X=0um,Y=0um : X=10.31mm,Y=3.13mm : 675um + 30um : 45um x 83um : 60um(Min) : 15um TYP. : Au
C63 C64
NJU6679
TERMINAL DESCRIPTION
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Terminal DUMMY0 DUMMY1 DUMMY2 DUMMY3 DUMMY4 DUMMY5 DUMMY6 DUMMY7 DUMMY8 DUMMY9 DUMMY10 DUMMY11 VDD P/S SEL86 RES VSS T2 T1 OSC1 OSC2 CS A0 WR RD D0 D1 D2 D3 D4 D5 D6(SCL) D7(SI) VSS VOUT C5+ C5C4+ C4C3+ C3C2+ C2C1+ C1VDD VR V5 V4 V3 X= um -4884 -4132 -4062 -3992 -3922 -3852 -3782 -3712 -3642 -3572 -3502 -3432 -3270 -3104 -2884 -2648 -2490 -2333 -2098 -1877 -1641 -1420 -1184 -954 -717 -481 -260 -40 180 400 621 841 1061 1222 1398 1468 1538 1608 1678 1748 1818 1888 1958 2028 2098 2168 2327 2582 2652 2722 Y= um -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405
Chip Size 10.31 x 3.13mm (Chip Center X=0um,Y=0um)
PAD No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Terminal V2 V1 VDD DUMMY12 DUMMY13 DUMMY14 DUMMY15 DUMMY16 DUMMY17 DUMMY18 DUMMY19 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 X= um 2792 2862 2932 3315 3385 3455 3525 3595 3665 3735 4884 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 4995 Y= um -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1405 -1416 -1356 -1296 -1236 -1176 -1116 -1056 -996 -936 -876 -816 -756 -696 -636 -576 -516 -456 -396 -336 -276 -216 -156 -96 -36 24 84 144 204 264 324 384 444 504 564 624 684 744 804 864
NJU6679
PAD No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Terminal C39 C40 C 41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C 51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C 61 C62 C63 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 X= um 4995 4995 4995 4995 4995 4995 4995 5010 4950 4890 4830 4770 4710 4650 4590 4530 4470 4410 4350 4290 4230 4170 4110 4050 3990 3930 3870 3810 3750 3690 3630 3570 3510 3450 3390 3330 3270 3210 3150 3090 3030 2970 2910 2850 2790 2730 2670 2610 2550 2490 Y= um 924 984 1044 1104 1164 1224 1284 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 PAD No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Terminal S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 X= um 2430 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 810 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -510 Y= um 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405
NJU6679
PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 Terminal S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 S85 S86 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96 S97 S98 S99 S100 S101 S102 S103 S104 S105 S106 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S117 S118 S119 S120 S121 S122 S123 S124 X= um -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 -2190 -2250 -2310 -2370 -2430 -2490 -2550 -2610 -2670 -2730 -2790 -2850 -2910 -2970 -3030 -3090 -3150 -3210 -3270 -3330 -3390 -3450 -3510 Y= um 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 PAD No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 Terminal S125 S126 S127 S128 S129 S130 S131 C127 C126 C125 C124 C123 C122 C121 C120 C119 C118 C117 C116 C115 C114 C113 C112 C111 C110 C109 C108 C107 C106 C105 C104 C103 C102 C101 C100 C99 C98 C97 C96 C95 C94 C93 C92 C91 C90 C89 C88 C87 C86 C85 X= um -3570 -3630 -3690 -3750 -3810 -3870 -3930 -3990 -4050 -4110 -4170 -4230 -4290 -4350 -4410 -4470 -4530 -4590 -4650 -4710 -4770 -4830 -4890 -4950 -5010 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 Y= um 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1405 1284 1224 1164 1104 1044 984 924 864 804 744 684 624 564 504 444 384 324 264 204 144 84 24 -36 -96 -156
NJU6679
PAD No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 Terminal C84 C83 C82 C81 C80 C79 C78 C77 C76 C75 C74 C73 C72 C71 C70 C69 C68 C67 C66 C65 C64 X= um -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 -4995 Y= um -216 -276 -336 -396 -456 -516 -576 -636 -696 -756 -816 -876 -936 -996 -1056 -1116 -1176 -1236 -1296 -1356 -1416
NJU6679
BLOCK DIAGRAM
C0 VSS VDD V1 to V5 5 COM Driver C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5SEG Driver COM Driver C63 S0 S131 C127 C64
Voltage Generator
Shift Register
Shift Register COM SEG Timing Generator
Display VR Output Assignment T1,T2 Register
Data
Latch
Row Address Decoder
Line Address Decoder
Counter Line
Display Data RAM
192 x 132
Buffer
Register
Culumn Address Decoder Display Culumn Address Counter Timing Generator Culumn Address Register OSC. OSC1 OSC2
Page
Address
I/O
Multiplexer
Instruction Decoder
Status
BF
Bus
Holder
Internal
Bus
Reset
MPU
Interface
RES CS A0
RD
SEL68 WR P/S
D0 to D7 (SI,SCL)
Start Line Register
NJU6679
TERMINAL DESCRIPTION No. 1,40 5,22 39 38 37 36 35 Symbol VDD VSS V1 V2 V3 V4 V5 I/O
Power
Function VDD=+3V LCD Driving Voltage Supplying Terminal. When the internal voltage booster is not used, supply each level of LCD driving voltage from outside with following relation. VDD>V1>V2>V3>V4>V5 When the internal power supply is on, the internal circuits generate and supply following LCD bias voltage from V1 to V4 terminals.
Bias 1/4Bias 1/5Bias 1/6Bias 1/7Bias 1/8Bias 1/9Bias 1/10Bias 1/11Bias 1/12Bias V1 V5+3/4VLCD V5+4/5VLCD V5+5/6VLCD V5+6/7VLCD V5+7/8VLCD V5+8/9VLCD V5+9/10VLCD V5+10/11VLCD V2 V5+2/4VLCD V5+3/5VLCD V5+4/6VLCD V5+5/7VLCD V5+6/8VLCD V5+7/9VLCD V5+8/10VLCD V5+9/11VLCD V3 V5+2/4VLCD V5+2/5VLCD V5+2/6VLCD V5+2/7VLCD V5+2/8VLCD V5+2/9VLCD V5+2/10VLCD V5+2/11VLCD V5+2/12VLCD V4 V5+1/4VLCD V5+1/5VLCD V5+1/6VLCD V5+1/7VLCD V5+1/8VLCD V5+1/9VLCD V5+1/10VLCD V5+1/11VLCD V5+1/12VLCD
GND VSS=0V
Power
V5+11/12VLCD V5+10/12VLCD
(VLCD=VDD-V5) 33,32, 31,30, 29,28, 27,26, 25,24 23 34 7 6 C1 ,C1 C2+,C2C3+,C3C4+,C4C5+,C5VOUT VR T1 T2
+ -
O
Step up capacitor connecting terminals. Voltage booster circuit (Maximum 6-time)
O I I
Step up voltage output terminal. Connect the step up capacitor between this terminal and VSS. Voltage adjust terminal. V5 level is adjusted by external bleeder resistance connecting between VDD and V5 terminal. LCD bias voltage control terminals. ( *:Don't Care)
T1 L H H T2 * L H V o lta g e b o o s t e r C ir. A v a ila b le N o t A v a il. N o t A v a il. V o lta g e A d j. A v a ila b le A v a ila b le N o t A v a il. V / F C ir. A v a ila b le A v a ila b le A v a ila b le
14 to 21
D0 to D7
(SI) (SCL)
I/O P/S="H" : Tri-state bi-directional Data I/O terminal in 8-bit parallel operation. P/S="L" : D7=Serial data input terminal. D 6=Serial data clock signal input terminal. Data from SI is loaded at the rising edge of SCL and latched as the parallel data at 8th rising edge of SCL. I Connect to the Address bus of MPU. The data on the D 0 to D7 is distinguished between Display data and Instruction by status of A0.
A0 Distin. H Display Dat a L Instruction
11
A0
4 10
RES CS
I I
Reset terminal. When the RES terminal goes to "L", the initialization is performed. Reset operation is executing during "L" state of RES. Chip select terminal. Data Input/Output are available during CS ="L".
NJU6679
No 13 Symbol RD(E) I/O I Function RD signal of 80 type MPU input terminal. Active "L" During this signal is "L" , D0 to D7 terminals are output. Enable signal of 68 type MPU input terminal. Active "H" Connect to the 80 type MPU WR signal. Actie "L". The data on the data bus input syncronizing the rise edge of this signal. The read/write control signal of 68 type MPU input terminal.
R/W State H Read L Write
12
WR(RW)
I
3
SEL68
I
MPU interface type selection terminal.
SEL68 S tate H 68 Type L 80 Type
2
P/S
I
serial or parallel interface selection terminal.
P/S "H" "L"
Chip Select Data/Command
Data D0 to D7 SI(D7)
Read/Write
serial Clock
CS CS
A A0
RD,WR Write Only
SCL(D6)
RAM data and status read operation do not work in mode of the serial interface. In case of the serial interface (P/S="L"),RD and WR must be fixed "H" or "L", and D0 to D5 are high impedance. 8 9 OSC1 OSC2 I O System clock input terminal for Maker testing.(This terminal should be Open) For external clock operation, the clock shoud be input to OSC1 terminal. LCD driving signal output terminals. Segmet output terminals:S 0 to S131 Common output terminals:C 0 to C127 Segment output terminal The following output voltages are selected by the combination of FR and data in the RAM.(non of the n-line inverse functions)
RAM Data H L FR H L H L Output Voltage Normal Reverse VDD V2 V5 V3 V2 VDD V3 V5
41 to 104 C0 to C63
105 to 236
S0
toS131
O
237 to 300
C64 to C127
O
Common output terminal The following output voltages are selected by the combination of FR and status of common.
Scan data H L FR H L H L Output Voltage V5 VDD V1 V4
NJU6679
Functional Description (1) Description for each blocks (1-1) Busy Flag (BF) While the internal circuits are operating, the busy flag (BF) is "1" and any instruction excepting for the status read are inhibited . The busy flag goes to "1" from D7 terminal when status read instruction is executed. D7 When enough cycle time over than tCYC indicated in " BUS TIMING CHARACTERISTICS" is ensured, no tCYC need to check the busy flag for reduction of the MPU loads. (1-2)Display Start Line Register The Display start Line Register is a pointer register which indicates the address in the Display Data RAM corresponding with COM0(normally it display the top line in the LCD Panel). This register also operates for COM0 vertical display scroll, the display page change and so on. The Display Start Line Set instruction sets the display start address of the Display Data RAM represented in 8-bit to this register. (1-3) Line Counter The Line Counter generates the line address of display data RAM by the count up operation synchronizing the common cycle after the reset operation at the status change of internal FR signal. (1-4) Column Address Counter The column address counter is 8-bit pre-settable counter addressing the column address of display data RAM as shown in Fig. 1. It is incremented (+1) up to (84)H by the Display Data Read/Write instruction execution. (84)H It stops the count up operation at (84)H, and it does not count up non existing address area over than (84)H by (84)H (84)H the count lock function. This count lock is released by new column address set. The column address counter is independent of the Page Register. By the Address Inverse Instruction, the column address decoder inverse the column address of Display Data RAM corresponding to the Segment Driver. (1-5) Page Register The page register gives a page address of Display Data RAM as shown in Fig. 1. When the MPU accesses the data with the page change, the page address set instruction is required. (1-6) Display Data RAM Display Data RAM is the bit map RAM consisting of 25,344 bits to memorize the display data corresponding to each pixel of LCD panel. The each bit in the Display Data RAM corresponds to the each pixel of the LCD panel and controls the display by following bit data. When Normal Display : On="1" , Off="0" When Inverse Display : On="0" , Off="1" The Display Data RAM outputs 132-bit parallel data in the area addressed by the line counter, and these data are set into the Display Data Latch. The access operation from MPU to the display data RAM and the data output from the display data RAM are so controlled to operate independently that the data rewriting does not influence with any malfunctions to the display.The relation between column address and segment output can inverse by the Address Inverse Instruction ADC as shown in Fig.1.
(1-7) Common Driver Assignment The scanning order can be assigned by mask option as shown on Table 1. Table 1
C O M O utp u t s Te rminals PAD No. V e r.A V e r.B 62 COM0 C O M 127 125 C 63 C O M 63 C O M 64 258 C 127 C O M 127 COM0 321 C 64 C O M 64 C O M 63
P in na m e C 0
NJU6679
P a g e A d d re s s D A TA D0 D1 D2
D 4 ,D 3 ,D 2 ,D 1 ,D 0
D i s p la y P a tte rn
Line Address
F o r e x a m p le the D i s p la y sta rt line i s 1 0H
00 01 02 Pege 0 03 04 05 06 07 08 09 0A Pege 1 0B 0C 0D 0E 0F 10 11 12 Pege 2 13 14 15 16 17 18 19
: : : : : : : :
D3 D4 D5 D6 D7 D0 D1 D2
(0,0,0,0,0)
D 4 ,D 3 ,D 2 ,D 1 ,D 0
D3 D4 D5 D6 D7 D0 D1 D2
(0,0,0,0,1)
C n Out C0 C1 C2 C3 C4 C5 C6 C7 C8 C9
: : : :
D 4 ,D 3 ,D 2 ,D 1 ,D 0
D3 D4 D5 D6 D7 D0 D1
(0,0,0,1,0)
: : : :
: : : :
D6 D7 D0 D1 D2
D 4 ,D 3 ,D 2 ,D 1 ,D 0
86 87 88 89 8A Pege 17 8B 8C 8D 8E 8F 90 91 92 Pege 18 93 94 95 96 97 98 99
: : : : : : : :
C 118 C 119 C120 C121 C122 C123 C124 C125 C126 C127
D3 D4 D5 D6 D7 D0 D1 D2
(1,0,0,0,1)
D 4 ,D 3 ,D 2 ,D 1 ,D 0
D3 D4 D5 D6 D7 D0 D1
(1,0,0,1,0)
: : : :
: : : :
D6 D7 D0 D1 D2
D 4 ,D 3 ,D 2 ,D 1 ,D 0
B6 B7 B8 B9 BA Pege 23 BB BC BD BE BF
| | | | | | | | | | |
7A 09
122
D3 D4 D5 D6 D7
(1,0,1,1,1)
|
7B 08
123
|
7C
|
7D
|
7E 05
126
|
7F 04
127
|
80 03
128
|
81 02
129
|
82 01
130
|
83 00
131
C o lum n Address
A D C
D 0="0" D 0="1"
00
01 02 03 04 05 06 07 08 09 81 80 2 3
7F 7E 7D 7C 7B 7A
83 82 0 1
07
124
06
125
S e g m e n t O utp u t
4
5
6
7
8
9
Fig.1 Correspondence with Display Data RAM Address
NJU6679
(1-8) Reset Circuit Reset circuit operates the following initializations when the condition of RES terminal goes to "L" level. Initialization 1 Display Off 2 Normal Display (Non-inverse display) 3 ADC Select : Normal (ADC Instruction D0 ="0") D0 4 Read Modify Write Mode Off 5 Internal Power supply (Voltage Booster) circuits Off 6 Static Drive Off 7 Driver Output Off 8 Clear the serial interface register 9 Set the address(00)H to the Column Address Counter address(00)H 10 Set the 1st Line in the Display Start Line Register.page (00)H to the Page Address Register (00)H 11 Set the page "0" to the Page Address Register 12 Set the EVR register to (FF)H (FF)H 13 Set the All display(1/128 duty) 14 Set the Bias select(1/12 Bias) 15 Set the 6-Time Voltage Booster 16 Set the n line turn over register (0)H (0)H The RES terminal should be connected to the Reset terminal of MPU for the initialization at the mean time with MPU as shown in "MPU Interface Example". The period of reset signal requires over than 10us RES="L" level input as shown in "Electrical Characteristics". After 1us from the rise edge of RES signal, the operation goes to normal. When the internal LCD power supply is not used, the external LCD power supply into the NJU6679 must be turned on during RES = "L". Although the condition of RES="L" clear each registers and initialize as above, the oscillation circuit and the output terminal conditions (D0 to D7) are not influenced. The initialization must be (D0 D7 performed using RES terminal at the power on, to prevent hung up or any incorrect operations. The reset Instruction performs the initialization procedures from No.9 to No.16 as shown in above. Note) The noise into the RES terminal should be eliminated to avoid the error on the application with the careful design. (1-9) LCD Driving (a) LCD Driving Circuits LCD driving circuits are consisted of 260 multiplexers which operate as 132 Segment drivers and 128 Common drivers. 128 Common drivers with the shift register scan the common display signal. The combination of the Display data, COM scan signal and FR signal form into the LCD driving output voltage. The output wave form is shown in the Fig. 7. (b) Display Data Latch Circuits Display Data Latch stores 132-bit display data temporarily which is output to LCD driver circuits at a common cycle from Display Data RAM addressed by Line Counter. The instructions of Display On/Off, Display inverse ON/OFF and Static Drive On/Off control only the data in Display Data Latch, therefore, the data in the Display Data RAM is not changed. (c) Line Counter and Latch signal of Latch Circuits The clock to Line Counter and latch signal to the Latch Circuits are generated from the internal display clock (CL). The line address of Display Data RAM is renewed synchronizing with display clock(CL). 132 bits display data are latched in display latch circuits synchronizing with display clock, and then output to the LCD driving circuits. The display data transfer to the LCD driving circuits is executed independently with RAM access by the MPU. (d) Display Timing Generator Display Timing Generator generates the timing signal for the display system by combination of the master clock CL and Driving Signal FR ( refer to Fig.2 ). The Frame Signal FR and LCD alternative signal generate LCD driving waveform of the two frame alternative driving method or n-Line inverse driving method.
NJU6679
(e)Common Timing Generation The common timing is generated by display clock. -Waveform of Display Timing(without the n-line inverse functions, the line inverse register in set to 0)
127 128 1 2 3 4 5 6 7 8 125 126 127 128 1 2 3 4 5
CL
FR
C0
VDD V1 V4 V5 VDD V1 V4 V5
C1
RAM DATA VDD V2 V3 V5
Sn
Fig.2 -Waveform of Display Timing(with the n-line inverse function, n=7, the line inverse register in set to 6)
127 128 1 2 3 4 5 6 7 8 125 126 127 128 1 2 3 4 5
CL
FR VDD V1 V4 V5 VDD V1 V4 V5
C0
C1
RAM DATA VDD V2 V3 V5
Sn
Fig.3
NJU6679
(f) Oscillation Circuit The Oscillation Circuit is a low power CR oscillator incorporating with Resistor and Capacitor. It generates clocks for display timing signal source and voltage booster circuits. The oscillation circuit output frequency is divided as shown in below for display clock CL. -The relation between duty and divide
Duty
1/8
1/16 1/24 1/32 1/40 1/48 1/56 1/64 1/72 1/80 1/88 1/96
1/104
1/112
1/120
1/128
Divide 1/64 1/32 1/21 1/16 1/12 1/10 1/9
1/8
1/7
1/6
1/5
1/4
(g) Power Supply Circuit Internal Power Supply Circuit generate the High voltage and Bias voltage for the LCD. The power Supply Circuit consists of Voltage Booster (6-Time maximum) Circuits, Regulator Circuits, and Voltage Followers. The internal Power Supply is designed for small size LCD panel, therefore it is not suitable for the large size LCD panel application. If the contrast is not good in the large size LCD panel application, please supply the external. The suitable values of the capacitors connecting to the V1 to V5 terminals and the voltage booster circuit, and V1 V5 the feedback resistors for V5 operational amplifier depend on the LCD panel. And the power consumption with V5 the LCD panel is depending on the display pattern. Please evaluate with actual LCD module. The operation of internal Power Supply Circuits is controlled by the Internal Power Supply On/Off Instruction. When the Internal Power Supply Off Instruction is executed, all of the voltage booster circuits, regulator circuits, voltage follower circuits are turned off. In this time, the bias voltage of V1, V2, V3, V4, and V5 for the V1 V2 V3 V4 V5 LCD should be supplied from outside, terminals C1+, C1-, C2+, C2-,C3+, C3-, C4+, C4-, C5+, C5- and VR should be open. The status of internal power supply is selected by T1 and T2 terminal. Furthermore the external T1 T2 power supply operates with some of internal power supply function.
T1 L H H
T2 L/H L H
Voltage Booster ON OFF OFF
Voltage Adj. ON ON OFF
Buffer(V/F) ON ON ON
Ext.Pow Supply VOUT V5,VOUT
C1+,C1- to C5+,C5Open Open
VR Term.
Open
When (T1, T2)=(H, L), C1+, C1-, C2+, C2-,C3+, C3-, C4+, C4-, C5+, C5- terminals for voltage booster circuits are (T1 T2 open because the voltage booster circuits doesn't operate. Therefore LCD driving voltage to the VOUT terminal VOUT should be supplied from outside. When (T1, T2)=(H, H), terminals for voltage booster circuits and VR are open, because the voltage booster (T1 T2 circuits and Voltage adjust circuits do not operate.
NJU6679
Power Supply applications (1)External power supply operation. (2)Internal power supply operation. (Voltage Booster, Voltage Adj., Buffer(V/F)) Internal power supply ON (instruction) (T1,T (T1,T2)=(L,L)
VDD T 1 V1 V2 V3
+
VDD T2
+
T 1 V1 T 2 C1+
+
V2
+
+
V3 V4
+
C1C2+ C2C3+ C3C4+ C4C5+ C5VR V5
+
V4 V5
+
+
V5 VOUT VSS VDD
+
VOUT VSS
+
(3)External power supply operation with Voltage Adjustment, Buffer(V/F) Internal power supply ON (Instruction) (T1,T2) = (H,L) (T1,T2
(4)External power supply operation adjusted Voltage to V5. Internal power supply (Instruction) (T1,T2) =(H,H) (T1,T2
VDD
+
VDD T 1
+
T 1 V1 T 2 V2 V3
V1 T 2
+ +
V2
+
+
V3
+ +
V4
+
V4 V5 VOUT VSS VR V5
V5 VO UT VSS VDD
: These switches should be open during the power save mode.
NJU6679
(2) Instruction The NJU6679 distinguishes the signal on the data bus by combination of A0, RD and WR. The decode of the instruction and execution performs depending on the internal timing only neither the external clock. In case of serial interface, the data input as MSB first serially. The Table. 4 shows the instruction codes of the NJU6679. (*:Don't Care) Table 4. Instruction Code
In s t r u c t i o n
A0 RD
WR
Code D
7
D 0
6
D
5
D 0
4
D
3
D
2
D
1
D
D e s c r i p ti o n
0
(1 )
D i s p la y O N /O F F D i s p la y S ta rt L i n e S e t H i g h O r d e r 4 b i ts D i s p la y S ta rt L i n e S e t L o w e r O r d e r 4 b its
0 0
1 1
0 0
1 0
1 0
1
1
1
0 1
L C D D i s p la y O N /O F F 0 :O F F 1 :O N D e te r m i n e t h e D i s p la y L i n e o f R A M to t h e C O M 0 . (S e t the H i g h e r o rd e r 4 b its ) D e te r m i n e t h e D i s p la y L i n e o f R A M to t h e C O M 0 . ( S e t t h e L o w e r o r d e r 4 b i ts ) S e t th e H i g h e r o r d e r 1 b i t p a g e o f D D R A M to t h e P a g e A d d r e s s R e g i s te r S e t th e L o w e r o r d e r 4 b i t p a g e o f D D R A M to t h e P a g e A d d r e s s R e g i s te r S e t th e H i g h e r o r d e r 4 b i t s C o l u m n A d d r e s s to t h e R e g . S e t th e L o w e r o r d e r 4 b its C o l u m n A d d r e s s to t h e R e g . R e a d o u t t h e i n te r n a l S ta t u s W r i t e t h e d a ta i n to t h e D i s p la y D a ta R A M R e a d t h e d a ta fro m t h e D i s p la y D a ta R A M
1
1
(2 )
H ig h O r d e r A d d re s s L o w e r O rd e r A d d re s s * * *
H i.
0
1
0
0
1
1
0
(3 )
P a g e A d d re s s S e t H i g h O r d e r 1 b i ts P a g e A d d re s s S e t L o w e r O r d e r 4 b its
0
1
0
0
1
0
0
0
1
0
1
1
0
0
L o w e r O rd e r P a g e A d d re s s H ig h O r d e r C o lum n A d d . L o w e r O rd e r C o lum n A d d . 0 0 0 0
(4 )
C o lum n A d d re s s S e t H i g h O r d e r 4 b i ts C o lum n A d d re s s S e t L o w e r O r d e r 4 b its
0 0 0 1 1 0
1 1 0 1 0 1
0 0 1 0 1 0
0 0
0 0
0 0
1 0
(5 ) (6 ) (7 ) (8 )
S ta t u s R e a d W r i t e D i s p la y D a ta R e a d D i s p la y D a ta N o r m a l o r In v e r s e o f O N /O F F S e t W h o le D i s p la y O N /N o r m a l D i s p la y S u b i n s t r u c t i o n ta b le mode P a r t i a l D i s p la y 1 s t B lo c k , S e t S ta rt d i s p la y u n i t 1 s t B lo c k , S e t The n u m b e r o f d i s p la y u n i ts 2 n d B lo c k , S e t S ta rt d i s p la y u n i t 2 n d B lo c k , S e t The n u m b e r o f d i s p la y u n i ts P a r t i a l d i s p la y o n
S ta t u s
W r i t e D a ta R e a d D a ta 1 0 1 0 0 1 1 0 1 0 1 0
In v e r s e t h e O N a n d O F F D i s p la y 0 :N o r m a l 1 :In v e r s e W h o le D i s p la y T u r n s O N 0 :N o r m a l 1 :W h o le D i s p . O N S e t th e S u b i n s t r u c ti o n ta b le .
(9 ) (1 0 ) (11 )
0 0
1 1
0 0
1 0
0 1
1 1
0 1
0 0
1 0
0 0
0 0
1 1
0 0
0 0
0 0
0 1
0
S ta rt d i s p la y unit
S e t th e S ta rt d i s p la y u n i t o f 1 s t B lo c k . S e t th e n u m b e r o f d i s p la y u n i t s o f 1 s t B lo c k . S e t th e S ta rt d i s p la y u n i t o f 2 n d B lo c k . S e t th e n u m b e r o f d i s p la y u n i t s o f 2 n d B lo c k . It c o m e s o ff th e m o d e to s e t a n d a d i s p la y i s e x e c u te d .
n u m b e r o f d i s p la y u n i ts 0 S ta rt d i s p la y unit
0 0
1 1
0 0
1 1
1 1
0 1
n u m b e r o f d i s p la y u n i ts 0 0 0 0 0
0
1
0
0
1
0
(1 2 )
n - li n e In v e r s e D r i v e Set R e g i s te r S e t H i g h e r o rd e r 2 b its R e g i s te r S e t L o w e r o rd e r 4 b its n - li n e In v e r s e D r i v e S e t i s e x e c u te d . 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 0 1 0 * * hig h e r o rd e r S e t th e n u m b e r o f i n v e r s e d r i v e lin e . S e t th e n u m b e r o f i n v e r s e d r i v e lin e . 0 T h e e x e c u t i o n o f th e li n e i n v e r s e d rive . S e t th e V 5 o u tp u t le v e l to t h e E V R r e g i s te r. (H i g h e r o r d e r 4 b i ts ) S e t th e V 5 o u tp u t le v e l to t h e E V R r e g i s te r. (L o w e r o r d e r 4 b i ts ) 0 1 T h e e x e c u t i o n o f th e E V R . It e n d s t h e s e ttin g o f s u b i n s t r u c t i o n ta b le .
L o w e r o rd e r 0 0
(1 3 )
E V R R e g i s te r S e t E V R R e g i s te r S e t H i g h e r o rd e r 4 b its E V R R e g i s te r S e t L o w e r o rd e r 4 b its E V R R e g i s te r S e t i s e xe c ute d . 0 1 0 1 0 0 0 E V R D a ta H ig h e r o rd e r E V R D a ta L o w e r o rd e r 0 0 0 0 0 0
0
1
0
1
0
0
1
0 0
1 1
0 0
1 0
0 1
1 1
0 1
(1 4 )
E n d o f s u b i n s truc tio n ta b le m o d e
NJU6679
(*:Don't Care)
Ins tructio n
A0 RD W R
Code D7 D6 D5 D4 D3 D2 1 0 0 0 1 1 1 1 0 D1 D0 0 0 1 1 0 0 B ias 0
D e s c rip ti o n S e le c t the b i a s ( 9 P a tte rns)
(15) (16)
B i a s S e le c t V o lta g e B o o s ter C ircuits Multiple S e le c t R e a d M o d i fy W rite /End Reset Inte rna l P o w e r Supply ON/OFF L C D D riving V o lta g e Set P o w e r Save (Dual Command) A D C S e le c t
B o o s t S e t the B o o s ter circuits Multiple (2 to 6 times)
(17) (18) (19) (20)
0 0 0 0
1 1 1 1
0 0 0 0
1 1 0 0
1 1 0 0
1 1 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 1 0 1
0 1 0
R e a d M o d i fy W rite m o d e D 0 = 0 :On D 0 = 1 :E nd Initia lize the i nte rna l C ircuits
0 0 :Int. P o w e r S u p p ly O F F 1 1 :Int. P o w e r S u p p ly O N 0 1 S e t LC D D riving Volta g e a fte r the i nte rna l (e xte rna l) p o w e r supply is turne d o n S e t the P o w e r S a v e M o d e (LC D D i s p la y O F F + W hole Display Turns ON)
(21)
(22)
0
1
0
1
0
1
0
0
0
0
0 1
S e t the D D R A M vs S e g m e nt D 0 = 0 :Normal D 0 = 1 :Inve rse
NJU6679
(3) Explanation of Instruction Code (3-1) Display On/Off This instruction executes whole display On/Off without relationship of the data in the Display Data RAM and internal conditions. R /W
A0 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 D
D 0:Display Off 1:Display On
(3-2) Display Start Line This instruction sets the line address of Display Data RAM corresponding the COM0 terminal (the highest position line of display in normal application). The display area is fixed automatically by number of display line which corresponds the display duty ratio from the pointed line address as the start line. This instruction realizes the vertical smooth scroll with extredisplay RAM or the page address change by dynamic line addressing. In this time, the contents of RAM are not changed.
A0 0 RD 1 R /W WR 0 D7 0 D6 1 D5 0 D4 1 D3 A7 D2 A6 D1 A5 D0 A4
0
1
0
0
1
1
0
A3
A2
A1
A0
A7 0 0
A6 0 0
A5 0 0
A4 0 0 : :
A3 0 0
A2 0 0
A1 0 0
A0 0 1
1
0
1
1
1
1
1
1
Line Address(HEX) 0 1 : : BF
(3-3) Page Address Set When MPU accesses the Display Data RAM, the page address must be selected before the data writing. The access to the Display Data RAM is available by the page and column address set (Refer the Fig. 1). The page address change does not influence with the display.
R /W WR 0
A0 0
RD 1
D7 0
D6 1
D5 0
D4 0
D3 *
D2 *
D1 *
D0 A4
0
1
0
1
1
0
0
A3
A2
A1
A0
(*:Don't Care)
A4 0 0
A3 0 0
A2 0 0 : :
A1 0 0
A0 0 1
Page 0 1 : :
1
0
1
1
1
23
NJU6679
(3-4) Column Address When MPU accesses the Display Data RAM, the page address (refer(3-3) ) and column address set are required before the data writing. The column address set requires twice address set which are higher order 4 bits address set and lower order 4 bits. When the MPU accesses the Display Data RAM sequentially, the column address is increase one by one automatically, therefore, the MPU can access only the data sequentially without address set. After writing 1page data, page address setting is required due to page address doesn't increase automatically. The increment of the column address is stopped at the address of (83)H automatically, and the page address is (83)H not changed even if the column address increase to (83)H and stop. In this time the page address is not (83)H changed.
A0 0 RD 1 R /W WR 0 D7 0 D6 0 D5 0 D4 1 D3 A7 D2 A6 D1 A5 D0 A4
Higher Order Lower Order
0 A7 0 0 A6 0 0
1 A5 0 0
0 A4 0 0
0 A3 0 0 : : 0
0 A2 0 0
0 A1 0 0 A0 0 1
0
A3
A2
A1
A0
1
0
0
0
0
1
1
Column Address(HEX) 0 1 : : 83
(3-5) Status Read This instruction reads out the internal status of "BUSY", "ADC", "ON/OFF" and "RESET".
R /W WR 1
A0 0
RD 0
D7 BUSY
D6 ADC
D5
ON/OFF
D4
RESET
D3 0
D2 0
D1 0
D0 0
BUSY
: BUSY=1 indicate the operating or the Reset cycle. The instruction can be input after the BUSY status change to "0". : Indicate the output correspondence of column (segment) address and segment driver. 0 :Counterclockwise Output (Inverse) Column Address 131-n <---> Segment Driver n 1 :Clockwise Output (Normal) Column Address n <---> Segment Driver n
ADC
(Note) The data "0=Inverse" and "1=Normal" of ADC is inverted with the ADC select Instruction of "1=Inverse" and "0=Normal". ON/OFF : Indicate the whole display On/Off status. 0 : Whole Display "On 1 : Whole Display "Off" (Note) The data "0=On" and "1=Off" of Display On/Off status read out is inverted with the Display On/Off instruction data of "1=On" and "0=Off". RESET : Indicate the initializing by RES signal or reset instruction. 0: 1 : Initialization Period
NJU6679
(3-6) Write Display Data This instruction writes the 8-bit data on the data bus into the Display Data RAM. The column address increases "1" automatically after data writing, therefore, the MPU can write the 8-bit data into the Display Data RAM continuously without any address setting after the start address setting.
A0 1 RD 1 R /W WR 0 D7 D6 D5 D4 D3 D2 D1 D0
W R I T E D ATA
(3-7) Read Display Data This instruction reads out the 8-bit data from Display Data RAM addressed by the column and page address. The column address increase "1" automatically after data reading out, therefore, the MPU can read out the 8bit data from the Display Data RAM without any address setting after the start address setting. One time of dummy read must operate after column address set as the explanation in "(5-4) Access to the Display Data RAM and Internal Register". In the serial interface mode, the display data is not read out.
A0 1 RD 0 R /W WR 1 D7 D6 D5 D4 D3 D2 D1 D0
R E A D D ATA
(3-8) Normal or Inverse On/Off Set This instruction changes the condition of display turn on and off as normal or inverse. The contents of Display Data RAM is not changed by this instruction execution.
A0 0 RD 1 R /W WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 D
D 0 : Normal 1 : Inverse
RAM data "1" correspond to "On" RAM data "0" correspond to "On"
(3-9) Whole Display On This instruction turns on the all pixels independent of the contents of Display Data RAM. In this time, the contents of Display Data RAM is not changed and kept. This instruction takes precedence over the "Normal or Inverse On/Off Set Instruction".
A0 0 RD 1 R /W WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 D
D 0 : Normal Display 1 : Whole Display turn on When Whole Display On Instruction is executed in the Display Off status, the internal circuits go to the power save mode (refer to the (s) Power Save).
NJU6679
(3-10) Sub Instruction table mode This instruction switches the instruction table from the main to the sub. The sub instruction table contains instructions of partial display, n-line inverse drive set and EVR register set as mentioned in (11), (12) and (13). The instruction of sub instruction table mode must be executed before above 3 sub instructions execution. The instruction of end of sub instruction table mode (14) switches the instruction table from the sub to the main. If any main instructions are written in the sub instruction mode, the NJU6679 will malfunction.
A0 0
RD 1
R /W WR 0
D7 0
D6 1
D5 1
D4 1
D3 0
D2 0
D1 0
D0 0
-Set sub Instruction table flow is shown below:
Sub Instruction table mode
Switches to Sub instruction table mode.
Set sub instructions.
End of Sub Instruction table mode.
Switches to Main instruction mode.
NJU6679
(3-11) Partial Display This instruction divides the active display area in a LCD panel to 16 units consisting of 8 commons per unit and displays one or two blocks of active display area consisting of a unit or more. In the partial display mode, the display duty ratio is set automatically according to the number of unit in a block or two. Therefore, the partial display function realizes to go down the LCD driving voltage according to the display duty ratio. As a result, the operation current of display system is much saved against the full display mode. The display units
UNIT UNIT UNIT UNIT UNIT UNIT UNIT UNIT UNIT UNIT UNIT UNIT UNIT UNIT UNIT UNIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (8 commons)
128-common
(8 commons)
132-segment Partial display instruction The partial display operates by the combination of instructions which area unit number of start position start unit block in the display area and a number of display unit from start position to end as a block. The number of block is set up to two.
A0 0 RD 1 R /W WR 0 D7 0 D6 0 D5 0 D4 0 D3 D D2 D D1 D D0 D
Start display unit The number of display units Start display unit The number of display units
1st Block
0
0
1
1 1
0
0 0
0
1 1
0
1 1
1
0 1
D
0 D
D
D D
D
D D
D
D D
D
D D
2nd Block
0
After execution of the next instruction, the display mode is changed to the partial display and the duty is changed automatically.
0 1 0 0 1 0 0 0 0 0 0
Partial display on
D :unit number (Hex.) Note) Incase of full display (1/128 duty), all of units on the display are selected when the first start unit is set to "0" (0,0,0,0) and the second number of display unit is set to "16" (1,0,0,0,0). In this time, the second block settings are ignored. In case of only one block display, the second block settings are ignored when the second start unit is set to "0" (0,0,0,0) and the second display unit number is set to "0" (0,0,0,0,0). Keep the order of partial display instruction sequence. Do not set over "UNIT 15" the display data in DD RAM are assigned continuously from page 0 for all of display block, even if non-display area is existed between the first block and the second.
NJU6679
The example of partial display setting UNIT 0 UNIT 1 UNIT 2 UNIT 3 UNIT 4 UNIT 5 UNIT 6 UNIT 7 UNIT 8 UNIT 9 UNIT 10 UNIT 11 UNIT 12 UNIT 13 UNIT 14 UNIT 15 The above partial display condition is set as follows: 1)Set sub instruction mode
A0 0 RD 1 R /W WR 0 D7 0 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0
1st Block
2nd Block
active display-block
Set sub instruction mode.
2)Set partial display conditions
A0 0 RD 1 R /W WR 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
1st Block, Set start display unit to "0" 1st Block, Set the number of display units to "2" 2nd Block, Set start display unit to "4" 2nd Block, Set the number of display units to "5" Partial display on.
0 0
0
0
1 1
1
1
0 0
0
0
0 1
1
0
0 1
1
1
1 0
1
0
0 0
0
0
0 0
0
0
0 1
1
0
1 0
0
0
0 0
1
0
In this case, 1/56 duty. (Duty=1/(number of display units x 8))
3)End sub instruction mode
A0 0 RD 1 R /W WR 0 D7 0 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1
End sub instruction mode. Back to main instruction mode.
Although the partial display instruction changes duty cycle ratio automatically and display area, LCD driving voltage, Bias and others are not changed. Therefore, the instruction of LCD driving voltage "OFF" (D=0) must be set before partial display operation, and the other instructions such as the n-line inverse drive set, EVR register set, bias select and voltage booster select should be set for optimum display-contrast. The "End of sub instruction mode" is required before these instructions in order to prevent momentary flickering.
NJU6679
-Set Partial Display flow is shown below:
Internal Power Supply OFF Sub Instruction Table Mode Partial Display n-line Inverse Drive Set EVR Register Set End Sub Instruction Table Mode Bias Select Voltage Booster Times Select Wait Time Internal Power Supply ON
(3-12) n-line Inverse Drive Mode This instruction sets a line number for inversion of LCD driving signal levels between "1" and "0". It reduces the stripe shadow(crosstalk) and stabilizes display quality. The n-line inverse number is set according to the n-line result of actual LCD panel display. The instructions must be input in order of followings. These instructions are sub instruction sets and must be set after (3-10)Sub instruction table mode.
A0 0 RD 1 R /W WR 0 D7 0 D6 1 D5 0 D4 1 D3 * D2 * D1 A5 D0 A4
Higher order Low order (*:Don't Care)
0
1
0
0
1
1
0
A3
A2
A1
A0
A5 0 0
A4 0 0
A3 0 0 : :
A2 0 0
A1 0 0
A0 0 1
Inverse line 2 : :
1
1
1
1
1
1
64
The actual operation starts after following instruction.
R /W WR 0
A0 0
RD 1
D7 0
D6 1
D5 1
D4 1
D3 0
D2 0
D1 0
D0 0
NJU6679
(3-13) EVR Register Set This instruction controls voltage adjustment circuits of internal LCD power supply and changes LCD driving voltage "V5". Finally, it adjusts the contrast of LCD display. By setting a data into EVR register, V5 output voltage selects one condition out of 201-voltage conditions. The range of V5 voltage is adjusted by setting V5 external resistors as mentioned in "(4)(b) Voltage Adjust Circuits". This instruction is sub instruction and it must be set after (3-10) Sub instruction table mode.
A0 0
RD 1
R /W WR 0
D7 1
D6 0
D5 0
D4 0
D3 A7
D2 A6
D1 A5
D0 A4
0 A7 0
1 A6 0
0 A5 1
1 A4 1 : :
0 A3 0
0 A2 1
1 A1 1
A3 A0 1
A2
A1 VLCD Low : : High
A0
1
1
1
1
1
1
1
1
VLCD=VDD-V5 LCD=VDD-V5 When EVR doesn't use, set the EVR register to (1,1,1,1,1,1,1,1).
The actual operation starts after following instruction.
A0 0 RD 1 R /W WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0
(3-14) End of Sub instruction table mode "End of sub instruction table mode" instruction switches instruction table from sub to main. (11)Partial display, (12)n-line inverse drive mode, and (13)EVR are sub instruction sets on the sub instruction table. The instruction of "END of sub instruction mode" must be set after these sub instruction sets. The NJU6678 may occur incorrect operation if any main instructions on the main instruction table are input in mode of sub instruction table.
A0 0 RD 1 R /W WR 0 D7 0 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1
NJU6679
(3-15) Bias Select This instruction decides the value of LCD driving voltage bias ratio. Especially, the bias shuld be selected for display quality in partial mode.
A0 0 RD 1 R /W WR 0 D7 1 D6 0 D5 1 D4 1 D3 A3 D2 A2 D1 A1 D0 A0
(*:Don't Care)
A3 0 0 0 0 0 0 0 0 1
A2 0 0 0 0 1 1 1 1 *
A1 0 0 1 1 0 0 1 1 *
A0 0 1 0 1 0 1 0 1 *
Bias 1/4 1/5 1/6 1/7 1/8 1/9 1/10 1/11 1/12
(3-16) Voltage Booster Circuit Multiple Select This instruction Selects a voltage boost time. The multiple must be selected the voltage boost times according to the maximum boost times by the external capacitors connections or less. Especially, the multiple should be selected for display quality and saving operation current in partial display mode.
A0 0 RD 1 R /W WR 0 D7 0 D6 0 D5 1 D4 1 D3 0 D2 A2 D1 A1 D0 A0
Commands A2 0 0 0 0 1 A1 0 0 1 1 * A0 0 1 0 1 *
Booster Multiple 6-Time External 5-Time External 4-Time External 3-Time External 2-Time External capacitors capacitors capacitors capacitors capacitors connections connections connections connections connections 2-Time 3-Time 2-Time 4-Time 3-Time 2-Time 5-Time 4-Time 3-Time 2-Time 6-Time 5-Time 4-Time 3-Time 2-Time
NJU6679
(3-17) Read Modify Write/End This instruction sets the Read Modify Write Mode for the column address increment control. In mode of the Read Modify Write, the column address increases "1" automatically when the Display Data Write Instruction is executed, but the address does not change when the Display Data Read Instruction is executed. This status is continued until End instruction execution. When the End instruction (D=1) is input, the column address goes back to the start address before the Read Modify Write instruction input. This function reduces the load of MPU for repeating the display data change in the fixed area (ex. cursor blink). D="1" to release the Read Modify Write mode and the column address back to the address where the read modify write mode setting.
A0 0 RD 1 R /W WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 D
D 0 : Read Modify Write On 1 : End Note) In mode of the Read Modify Write, any instructions except for Column Address Set can execute.
- Sequence of cursor blink display
Page Address Set Column Address Set Set to the Start Address of Cursor Display
Read Modify Write
Start the Read Modify Write Read the Data as dummy
Dummy Read Data Read
Data inverse by MPU Data Write Dummy Read Data Read Data Write
End
End the Read Modify Write
NO Finish? YES
NJU6679
(3-18) Reset This instruction executes the following initialization. Initialization (1) Set the Address (00)H into the Column Address Counter. (00)H (2) Set the Address (00)H into the Display Start Line Register. (00)H (3) Set the page "0" into the Page Address Register. (4) Set 0 to the EVR Register to (FF)H. (FF)H (5) Set the All display(1/128 duty) (6) Set the Bias select(1/12 Bias) (7) Set the 6-Time Voltage Booster. (8) Set the n-line inverse register (0)H (0)H In this time, the Display Data RAM is not influenced.
R /W WR 0
A0 0
RD 1
D7 1
D6 1
D5 1
D4 0
D3 0
D2 0
D1 1
D0 0
The reset signal input to the RES terminal (hardware reset) must be input for the power on initialization. Reset instruction does not perform completely in stead of hardware reset using the RES terminal.
(3-19) Internal Power Supply ON/OFF This instruction set the condition of internal Power Supply On/Off. Voltage Booster circuits, Voltage Regulator and Voltage Follower operate at On. To operate the voltage booster circuits, the oscillation circuits must be operating.
A0 0 RD 1 R /W WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 D
D 0 : Internal Power Supply Off 1 : Internal Power Supply On The internal Power Supply must be Off when external power supply using. *1 The set up period of internal power supply On depends on the step up capacitors, voltage stabilizer capacitors, VDD and VLCD. Therefore it requires the actual evaluation using the LCD module to get the correct time. (Refer to the (4)(d) Fig.4)
NJU6679
(3-20) LCD Driving Voltage Set This instruction controls LCD driving waveform output through the COM/SEG terminals.
A0 0 RD 1 R /W WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 D
D 0 : LCD driving waveform output Off 1 : LCD driving waveform output On The NJU6679 contains low power LCD driving voltage generator circuit reducing own operation current. Therefore, it requires the following sequence procedures at power on for the power source stabilized operation.
- LCD driving power supply ON/OFF sequences The following sequences are required when the power supply is turned On/Off. When the power supply is turned on again after the turn off (by the power save instruction), the power save release sequence ((3-21) Power Save) is required. Turn ON sequence
Output Assign. Register Set EVR Register Set Internal Power Supply ON or External Power supply ON (Wait Time) *1 LCD Driving Voltage Set to ON
Turn OFF sequence
Display OFF Whole Display ON Internal Power Supply OFF or External Power Supply OFF LCD Driving Voltage Set to OFF
*1 The wait time depends on the C1 to C9, COUT capacitors (refer (4) (d)Fig.4), VDD and VLCD voltage. C1 C9 COUT VDD VLCD Therefore it requires the actual evaluation using the LCD module to get the correct time. (Refer to the following graph.)
The wait time [Typical performance]
100 80 Time[ms] 60 40 20 0 0 0.2 0.4 0.6 C3 to C7[uF] 0.8 1 1.2
T.B.D.
Cout=1 to 4.7[uF]
VDD=2.7V,VLCD=7V,Ta=25C
NJU6679
(3-21) Power Save(Dual Command) When both of Display Off and Whole Display On are executed, the internal circuits go to the power save mode and the operating current is reduced as some as the stand by current. The internal status in the Power Save Mode is shown in follows; (1) Stop the Oscillation Circuits and Internal Power Supply Circuits operation. (2) Stop the LCD driving. Segment and Common drivers output VDD level. VDD (3) Keep the display data and operating mode just before the power save mode. (4) All of LCD driving bias voltage fix to the VDD level. VDD The power save and its release perform according to the following sequences. Power Save Sequence
Display OFF Whole Display ON LCD Driving Voltage Set to OFF
Power Save Release Sequence
Normal Display Display ON (Wait Time) LCD Driving Voltage Set to ON
(Whole Display OFF)
*1 In the power save sequence, the power save mode is started after the second instruction "whole Display ON". *2 In the power save release sequence, the power save mode is released after the Normal Display instruction (Whole display OFF). The instruction of display ON is input at any timing after the instruction of normal display in power save release sequence. *3 Until "LCD driving voltage set to ON" execution, NJU6679 operating current is higher than usual state and all COM/SEG terminals output VDD level continuously. VDD *4 In case of the external power supply for LCD driving, it should be turned off and made condition like as unconnection or connected to VDD before the power save mode or at the same time. In this time, VOUT VDD VOUT terminal should be made condition like as disconnection or connected to the lowest voltage of the system (V5 (V5 level from the external power supply). (3-22) ADC Select This instruction set the correspondence of column address in the Display Data RAM and segment driver output. (See Fig. 1.) By this instruction, the order of segment output can be changed by the software, and no restriction of the LSI placement against the LCD panel.
A0 0 RD 1 R /W WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 D
D 0 : Clockwise Output (Normal) 1 : Counterclockwise Output (Inverse)
NJU6679
(4) Internal Power Supply (a) 6-time voltage booster circuits 6-time voltage booster circuits connecting five capacitors between C1+ and C1-, C2+ and C2-, C3+ and C3-, C4+ and C4-, C5+ and C5-, VSS and VOUT boost the voltage of VDD - VSS to negative voltage (VDD Common) and VSS VOUT VDD VSS (VDD output the boosted voltage from the VOUT terminal. It selects one of boost time from 2 to 6 times by external VOUT capacitors connection. Furthermore, it also selects one of boost time by "Voltage Booster circuits multiple select" instruction. The boost voltage and the voltage booster circuits are shown in below. Voltage Booster circuits requires the clock signals from internal oscillation circuit, therefore, the oscillation circuits must be operating when voltage boost operation. The boost voltage times are shown in below. When 6-time voltage boost operation, the operation voltage of VDD-VOUT should be less than 18V. VDD-VOUT
VDD=+3V VSS=+ VSS=+0V VOUT=-VDD=-3V VOUT=-2VDD=-6V VOUT=-3VDD=-9V VOUT=-4VDD=-12V VOUT=-5VDD=-15V
2-time voltage
3-time voltage
4-time voltage
5-time voltage
6-time voltage
Examples for connecting the capacitors
VSS C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT + + + + + + VSS C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT + + + + + VSS C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT + + + +
6-time voltage
VSS C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT
5-time voltage
VSS C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT
4-time voltage
+ + +
+
+
3-time voltage
2-time voltage
NJU6679
(b)Voltage Adjust Circuits The boosted voltage of VOUT output from V5 through the voltage adjust circuits for LCD driving. The output VOUT V5 voltage of V5 is adjusted by changing the Ra and Rb within the range of | V5 | < | VOUT |. The output voltage V5 V5 VOUT is calculated by the following formula. VLCD = VDD-V5 = (1+Rb/Ra)VREG VDD-V5 (1+Rb/Ra)VREG
(1)
VDD VREG Ra R1 VR R2 V5 R3
Rb
Fig. 3 The voltage of VREG is a standard voltage produced from built-in bleeder resistance. VREG is possible to be VREG VREG fine-adjusted by EVR functions mentioned in (c). For fine-adjustment of V5, R2 as variable resistor, R1 and R3 as fixed constant should be connected to VDD VDD terminal, VR and V5, as shown in Fig.3. V5,
[ Design example for R1, R2 and R3 / Reference ] - R1+R2+R3=5M (Determined by the current flown between VDD-V5) R1+R2+R3=5M VDD-V5 - Variable voltage range by the R2. -6V to -7.5V (VLCD=VDD-V5 --> 9.0V to 10.5V) (VLCD=VDD-V5 (Determined by the LCD electrical characteristics) - VREG=3V(In case of EVR=(FF)H) VREG=3V(In EVR=(FF)H - R1, R2 and R3 are calculated by above conditions and the formula of (1) to below; R1=2.0M R2=0.5M R3=2.5M R1=2.0M, R2=0.5M, R3=2.5M * If the power supply voltage between VDD and VSS changes, V5 changes too. Therefore the power supply VDD VSS V5 voltage should be stabilized for V5 stable operation. V5
NJU6679
(c) Contrast Adjustment by the EVR function The EVR controls voltage of VREG by instruction and changes voltage of V5. VREG V5 As result, LCD display contrast is adjusted by V5. The EVR selects a voltage of VREG in the following 201 V5 VREG conditions by setting 6bits data into the EVR register. In case of EVR operation, T1 terminal and T2 require to set couples of value as (L,L),(L,H) and (H,L) excepting T1 T2 for (H,H) and the internal power supply must turn on by instruction. (37)H to (4F)H available for use. If keeping 3% precision set EVR over (4F)H.
EVR register
:
VREG[V] (124/300) x (VDD-VSS) : : : (298/300) x (VDD-VSS) (299/300) x (VDD-VSS) (300/300) x (VDD-VSS)
VLCD Low : : : : : High
(4F)H : : : (FD )H (FE)H (FF)H
(0,1,0,0,1,1,1,1) : : : (1,1,1,1,1,1,0,1) (1,1,1,1,1,1,1,0) (1,1,1,1,1,1,1,1)
Adjustable range of the LCD driving voltage by EVR function The adjustable range is decided by the power supply voltage VDD and the ratio of external resistors VDD Ra and Rb. [ Design example for the adjustable range / Reference ] - Condition VDD=3.0V, VSS=0V VDD=3.0V, VSS=0V Ra=1M Rb=4M Ra=1M, Rb=4M ( Ra:Rb=1:4 ) The adjustable range and the step voltage are calculated as follows in the above condition. In case of setting (4F)H in the EVR register, (4F)H VLCD = ((Ra+Rb)/Ra)VREG ((Ra+Rb)/Ra)VREG = (5/1) x [(100/300) x 3.0] = 6.2V In case of setting (FF)H in the EVR register, (FF)H VLCD = ((Ra+Rb)/Ra)VREG ((Ra+Rb)/Ra)VREG = (5/1) x [(300/300) x 3.0] = 15.0V
Min.(4F)H Adjustable Range Step Voltagre 6.2 ------------------50 Max.(FF)H 15.0 [V] [mV]
* In case of VDD=3V VDD=3V
NJU6679
*) The VLCD operating temperature. Please refer to the following graphs. VLCD (conditions) VDD = 3V VDD Ra=1M Rb=4M Ra=1M, Rb=4M ( Ra:Rb = 1:4 ) Five times voltage
VLCD vs. Temperature (Typical Performance)
16 14 12 10 8 6 4 2 0
-30 -20 -10 0
VLCD [V]
T.B.D T.B.D.
10 20 30 40 50 60 70 80
VLCD EVR=(FF)H VLCD EVR=(4F)H
Ta [oC]
NJU6679
(d) LCD Driving Voltage Generation Circuits The LCD driving bias voltage of V1,V2,V3,V4 are generated internally by dividing the V5 voltage with the V1,V2,V3,V4 V5 internal bleeder resistance. And it is supplied to the LCD driving circuits after the impedance conversion with voltage follower circuit. As shown in Fig. 4, Five capacitors are required to connect to each LCD driving voltage terminal for voltage stabilizing. And the value of capacitors C6, C7, C8, C9 and C10 are determined depending on the actual LCD panel display evaluation. Using the internal Power Supply
VSS C1
Using the external Power Supply
VSS C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5-
+ +
C1+ C1C2+ C2-
C2 COUT
+
C3
+ + +
C3+ C3C4+ C4C5+ C5VOUT
C4
C5
NJU6679
VOUT
NJU6679
R3 V5 V5
R2
VR
VR
R1 VDD VDD V1
+ C6 + C7 + C8 + C9 + C10
V1 V2 V3 V4 V5
External Voltage Generator
V2 V3 V4 V5
Reference set up value VLCD=VDD-V5 = 9.0 to 10.5V
COUT C1 to C5 C6 to C10 R1 R2 R3 to 1.0uF to 1.0uF T.B.D. 2.0M 0.5M 2.5M
Fig.4 *1 Short wiring or sealed wiring to the VR terminal is required due to the high impedance of VR terminal. *2 Following connection of VOUT is required when external power supply using. VOUT When VSS > V5 --- VOUT=V5 VSS V5 VOUT=V5 When VSS < V5 --- VOUT=VSS VSS V5 VOUT=VSS
NJU6679
(5) MPU Interface (5-1) Interface type selection NJU6679 interfaces with MPU by 8-bit bidirectional data bus (D7 to D0) or serial (SI:D7). The 8 bit parallel or (D7 D0 (SI:D7 serial interface is determined by a condition of the P/S terminal connecting to "H" or "L" level as shown in Table 5. In case of the serial interface, status and RAM data read out operation is impossible. Table 5
P /S H L Type P a rallel S e rial CS CS CS A0 A0 A0 RD RD WR WR SEL68 SEL68 D7 D7 SI D6 D6 SCL
D 0 to D5 D 0 to D5
Hi-Z
(5-2) Parallel Interface The NJU6679 interfaces to 68 or 80 type MPU directly when the parallel interface (P/S="H") is selected. 68 type MPU or 80 is determined by the condition of SEL68 terminal connecting to "H" or "L" as shown in table 6. Table 6
SEL68
H L
Typ e 6 8 typ e M P U 8 0 typ e M P U
CS CS CS
A0 A0 A0
RD E RD
WR R/W WR
D 0 to D 7 D 0 to D 7 D 0 to D 7
(5-3) Discrimination of Data Bus Signal The NJU6679 discriminates the mean of signal on the data bus by the combination of A0, E, R/W, and (RD,WR) signals as shown in Table 7. Table 7
Common A0 1 1 0 0 68 type R/W 1 0 1 0 RD 0 1 0 1 80 type WR 1 0 1 0 Function Read Display Data Write Display Data Status Read Write into the Register(Instruction)
(5-4) Serial Interface.(P/S="L") Serial interface circuits consist of 8 bits shift register and 3 bits counter. SI and SCL input are activated when the chip select terminal CS set to "L"and P/S terminal set to "L". The 8 bits shift register and 3 bits counter are reset to the initial condition when the chip is not selected. The data input from SI terminal is MSB first like as the order of D7,D6,- - - - D0, and the data are entered into the shift register synchronizing with the rise edge of D7,D6 D0, the serial clock SCL. The data in the shift register are converted to parallel data at the 8th serial clock rise edge input. Discrimination of the display data or instruction of the serial input data is executed by the condition of A0 at the 8th serial clock rise edge. A0="H" is display data and A0="L" is instruction. When RES terminal becomes "L" or CS terminal becomes "H" before 8th serial clock rise edge, NJU6679 recognizes them as a instruction data incorrectly. Therefore a unit of serial data must be structured by 8-bit. The time chart for the serial interface is shown in Fig. 5. To avoid the noise trouble, the short wiring is required for the SCL input. Note) The read out function, such as the status or RAM data read out, is not supported in this serial interface .
CS SI SCL A0 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 D7 D6 10
Fig. 5
NJU6679
(5-5) Access to the Display Data RAM and Internal Register. The NJU6679 is operating as one of pipe-line processor by the bus-holder connecting to the internal data bus to adjust the operation frequency between MPU and the Display Data RAM or Internal Register. For example, when the MPU reads out the data from the Display Data RAM, the read out data in the data read cycle (dummy read) is held in the bus-holder, then it is read out from the bus-holder to the system bus at the next data read cycle. When the MPU writes the data into the Display Data RAM, the data is held in the busholder, then it is written into the Display Data RAM by the next data write cycle. Therefore high speed data transmission between MPU and NJU6679 is available because of it is not limited by the tACC and tDS as display data RAM access time and is limited by the system cycle time (R) or (W). tACC tDS If the cycle time is not be kept in the MPU operation, NOP should be inserted to the system instead of the waiting operation. The read out operation does not read out the data in the pointed address just after the address set operation. And second read out operation can read out the data correctly from the pointed address. Therefore, one dummy read operation is required after address setting or write cycle as shown in FIG. 6. Write Operation
MPU WR DATA N N+1 N+2 N+3
Internal Timing
I/O Buffer WR
N
N+1
N+2
N+3
Read Operation
MPU WR RD DATA N
Address Set N
N
Dummy Read
n
Data Read n
n+1
Data Read n+1
Internal Timing
WR RD Column Address I/O Buffer N N n N+1 n+1 N+2 n+2
Fig.6 (5-6) Chip Select CS is Chip Select terminal. In case of CS="L", the interface with MPU is available. In case of CS="H", the D0 D0 to D7 are high impedance and A0, RD, WR, D7(SI) and D6(SCL) inputs are ignored. If the serial interface is D7 D7 D6 selected when CS="H",the shift register and the counter are reset. However, the reset is always operated in any conditions of CS.
NJU6679
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (1) Supply Voltage (2) Supply Voltage (3) Input Voltage Operating Temperature Storage Temperature SYMBOL VDD V5 V1 to V4 VIN Topr Tstg RATINGS -0.3 to +5.0 VDD-18.0 to VDD+0.3 V5 to VDD+0.3 -0.3 to VDD+0.3 -30 to +80 -55 to +125 (Chip) -55 to +100 (TCP)
(Ta=25 (Ta=25C)
UNIT V V V V C C
Note 1) If the LSI are used on condition above the absolute maximum ratings, the LSI may be destroyed. Using the LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electric characteristics conditions will cause malfunction and poor reliability. Note 2) All voltage values are specified as VSS=0 V. VSS=0 Note 3) The relation : VDD > V1 > V2 > V3 > V4 > V5 ; VDD > VSS > VOUT must be maintained. VDD V1 V2 V3 V4 V5 VDD VSS VOUT Note 4) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for VDD VSS the voltage converter. (VDD=2.7V to 3.3V, VSS=0V, Ta=-30 to +80C) +80
MIN. 2.4 VDD-18.0 VLCD= VDD-V5 D0...D 7,A0, CS,RES,RD,WR,SEL68, P/S Terminals D0...D 7 IOH=-0.5mA Terminals IOL= 0.5mA All Input terminals VLCD=15.0V VLCD=8.0V during Power save Mode Display VLCD=15.0V Accessing f C YC =200kHz Ta=25C
VDD-0.5VLCD
ELECTRICAL CHARACTERISTICS (1)
PARAMETE Operating Voltage(1) OperatingVoltage(2) Input Voltage Output Voltage High Level Low Level High Level Low Level Current Driver On-resistance Stand-by Current Operating Current
SYMBOL
C O N D ITIO N S
TYP.
VDD V5 V1,V2 V3,V4 VIHC1 VILC1 VOHC11 VOLC11 ILIO RON1 RON2 IDDQ IDD12 IDD21
MAX. 3.6 VDD-6.0 VDD
VDD-0.5VLCD
UNIT Note V 5 V V V V V uA kW uA uA 6 7 8 9
V5 0.8VDD VSS 0.8VDD VSS - 1.0 2.0 3.0 T.B.D. T.B.D. T.B.D.
VDD 0.2VDD VDD 0.2VDD 1.0 3.0 4.5 T.B.D. T.B.D. T.B.D.
Input Leakage
NJU6679
PARAMETER Input Terminal Capacitance Oscillation Frequency Output Volt.
SYMBOL
CIN fOSC
C O N D ITIONS A0,CS,RES,RD,WR,SEL68, P/S,T1,T2,D0...D7 Ta=25C
MIN
TYP 10 T.B.D.
MAX
UNIT Note pF kHz
Ta=25C VSS-Vout, 6-time voltage booster, VOUT1 VDD=3V DC/DC VOUT2 V5 IOUT1 Voltage Adjustment Circuit "OFF" VDD=3V, VLCD=12V COM/SEG Terminals Open No Access Display Checkered pattern VDD=3V;C OUT=4.7uF 6-time voltage booster Voltage Booster Circuit "OFF"
VDD-15.0 2000 VDD-18.0V VDD-18.0V T.B.D. T.B.D. T.B.D.
VDD-15.5 4000 VDD-6.0V VDD-6.0V T.B.D. T.B.D. T.B.D. T.B.D.
V V 10 V
On-resistance
Adjustment range of LCD
Voltage Driving Volt. Booster Voltage
Follower Operating Current Voltage Reg.
IOUT2 IOUT3
uA %
11 12
VREG% VDD=3V,Ta=25C, VREG=4F to FFH
Note 5) NJU6679 can operate wide operating range, but it is not guarantee immediate voltage changing during the accessing of the MPU. Note 6) Apply to the High-impedance state of the D0 to D7 terminals. D0 D7 Note 7) RON is the resistance values between power supply terminals(V1, V2, V3, V4) and each output RON terminals(V1 V2 V3 V4 terminals of common and segment supplied by 0.1V. This is specified within the range of supply voltage (2). Note 8,9,11) Apply to current after "LCD Driving Voltage Set". Note 8) Apply to the external display clock operation in no access from the MPU and no use internal power supply circuits. Note 9) Apply to the condition of cyclic (tcyc) inverted data input continuously in no use internal power supply circuits. The operating current during the accessing is proportionate to the access frequency. In the no accessing period, it is as same as IDD1X. IDD1X. Note 10) LCD driving voltage V5 can be adjusted within the voltage follower operating range. V5 Note 11) Each operating current of voltage supply circuits block is specified under below table conditions.
Status SYMBOL IOUT1 IOUT2 IOUT3 T1 L H H T2 * L H Internal Oscillator Validity Validity Validity
Operating Condition Voltage Voltage Booster Adjustment Validity Validity Invalidity Validity Invalidity Invalidity
Voltage Follower Validity Validity Validity
External Voltage Supply (Input Terminal) Unuse Use(VOUT) Use(VOUT,V5)
(* = Don't Care) Note 12) Apply to the precision of the voltage between VDD and V5 with EVR function. VDD V5
NJU6679
MEASUREMENT BLOCK DIAGRAM :IOUT1 :IOUT1
VDD VR V5
A
VSC S 1+ + +
NJU6679
C 1-C2 + + C 2- C + 3 + C 3-C4 + + C 4-C 5+ + C 5-
T 1 T 2 VU OT
:IOUT2 :IOUT2
VDD VR V5
A
1+ VSC S +
NJU6679
C 1-C2 + + C2- C + 3 + C 3-C4 + + C4-C 5+ + C 5-
T 1 T 2 VU OT
:IOUT3 :IOUT3
VDD VR V5
A
VSC S 1+ +
NJU6679
C 1-C2 + + C2- C + 3 + C 3-C4 + + C4-C 5+ +
T 1 T 2 C VU 5- O T
ELECTRICAL CHARACTERISTICS (2)
P A R A M E T E R SYMBOL CONDITIONS Reset time tR RES Terminal Reset "L" Level Pulse tRW RES Terminal Width
(VDD=2.7V to 3.3V, VSS=0V, Ta=-30 to +80C) +80
MIN 1.0 10 TYP MAX UNIT Note us 13 us 14
Note 13) Specified from the rising edge of RES to finish the internal circuit reset. Note 14) Specified minimum pulse width of RES signal. Over than tRW "L" input should be required for correct tRW reset operation.
NJU6679
BUS TIMING CHARACTERISTICS - Read/Write operation sequence (80 Type MPU)
tCYC8 A0,CS tAW8 tCCL tCCH tDS8 D0 to D7 (Write) tf tACC tDH8 tAH8
WR,RD
tr tCH8
D0 to D7 (Read)
(VDD= (VDD=2.7V to 3.3V,Ta=-30 to +80C) 3.3V,Ta=-30 +80
PARAMETER A d d r e s s H o ld Ti m e A d d ress S e t Up Time S ystem C ycle W R Ti m e RD W R ,"L" C o ntro l R D ,"P uls e W i d th L" "H" D a ta S e t U p T i m e D a ta H o ld Ti m e R D A c c e s s Ti m e Output D i s a b le Ti m e R i s e Ti m e , Fall Time A 0 ,C S Te rminals S YMBOL tA H 8 tA W 8 tC YC 8 (W) tC YC 8 ( R ) tC C L ( W ) tC C L ( R ) tC C H tD S 8 tD H 8 tA C C 8 tC H 8 tr,tf M IN . TYP. 10 0 220 350 50 200 160 35 15 120 15 15 MAX. C O N D ITIO U N IT N ns ns ns ns ns ns ns ns ns ns ns ns
W R ,RD Te rminals
D 0 to D 7 Te rminals C S , WR, R D ,A 0 , D 0 to D 7 Te rminals
CL=100pF
Note 15) Rise time (tr) and fall time (tf) of input signal should be less than 15ns. (tr (tf Note 16) Each timing is specified based on 0.2xVDD and 0.8xVDD. 0.2xVDD 0.8xVDD.
NJU6679
- Read/Write operation sequence (68 Type MPU)
tCYC6 tEWL E tAW6 R/W tr tEWH tf tAH6 A0,CS tDS6 D0 to D7 (Write) tACC6 D0 to D7 (Read) tOH6 tDH6
(VDD= (VDD=2.7V to 3.3V,Ta=-30 to +80C) 3.3V,Ta=-30 +80
PARAMETER SYMBOL Address Hold Time tAH6 Address Set Up Time tAW6 A0,CS,R/W Terminals tCYC6(W) System Cycle Time(W) System Cycle Time(R) tCYC6(R) Read"H" tEWH Enable Write"H" E Terminal Pulse Width "L" tEWL Data Set Up Time tDS6 Data Hold Time tDH6 D0 to D7 Terminals Access Time tACC6 Output Disable Time tOH6 A0, CS, R/W, Rise Time, Fall Time E, D0 to D7 tr,tf Terminals MIN. TYP. 10 0 220 350 200 50 160 35 15 150 20 15 MAX. CONDITION UNIT ns ns ns ns ns ns ns ns ns ns ns
CL=100pF
Note 17) tCYC6 indicates the E signal cycle during the CS activation period. The System Cycle Time must be tCYC6 required after CS becomes active. Note 18) Rise time (tr) and fall time (tf) of input signal should be less than 15ns. (tr (tf Note 19) Each timing is specified based on 0.2xVDD and 0.8xVDD. 0.2xVDD 0.8xVDD.
NJU6679
- Write operation sequence (Serial Interface)
tCSS CS
tCSH
tSAS A0 tSCYC tSLW SCL tSDS SI tf tr
tSAH
tSHW tSDH
(VDD= (VDD=2.7V to 3.3V,Ta=-30 to +80C) 3.3V,Ta=-30 +80
PARAMETER Serial Clock cycle SCL SCL "H" pulse width Terminal SCL "L" pulse width Address Set Up Time A0 Terminal Address Hold Time Data Set Up Time SI Terminal Data Hold Time CS-SCL Time SYMBOL tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS CS Terminal tCSH SCL, A0, CS, SI tr,tf Terminals MIN. TYP. 60 30 30 0 150 25 10 10 300 15 MAX. CONDITION UNIT ns ns ns ns ns ns ns ns ns ns
Rise Time, Fall Time
Note 20) Rise time (tr) and fall time (tf) of input signal should be less than 15ns. (tr (tf Note 21) Each timing is specified based on 0.2xVDD and 0.8xVDD. 0.2xVDD 0.8xVDD. Note 22) In case of instruction set continuously, it is required to wait more than 450ns between the instruction and next as follows. SCL 8th clock SCL 1st clock
SCL
Instruction N
450 ns SCL"L"pulse width (Between the instruction and next)
Instruction N+1
NJU6679
LCD DRIVING WAVEFORM
0
1
2
3
4
126 127
0
1
2
3
4
5
126 127
VDD
FR COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
VSS
VDD V1 V2
COM0
V3 V4 V5
VDD V1 V2 COM1 V3 V4 V5
COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15
VDD V1 V2 COM2 V3 V4 V5
SE G0
SE G1
SE G2
SE G3
SE G4
VDD V1 V2 SEG0 V3 V4 V5 VDD V1 V2 SEG1 V3 V4 V5
V5 V4 V3 V2 V1 COM0-SEG0 VDD
-V1 -V2 -V3 -V4 -V5
V5 V4 V3 V2 V1 COM0-SEG1 VDD
-V1 -V2 -V3 -V4 -V5
Fig.7
NJU6679
APPLICATION CIRCUIT - Microprocessor Interface Example The NJU6679 interfaces to 80 type or 68 type MPU directly. And the serial interface also communicate with MPU.
- 80 Type MPU
VCC A0 A0 VDD CEL86 A0 to A7 IORQ CS
Decoder NJU6679
MPU
D0 to D7 RD WR GND RES RD WR RES
D0 to D7
P/S VSS
RESET
- 68 Type MPU
VCC VDD CEL86 A0 to A15 VMA CS
A0
A0
Decoder NJU6679
D0 to D7 E R/W RES VSS P/S
MPU
D0 to D7 E R/W GND RES
RESET
- Serial Interface
VCC VDD CEL86 A1 to A7 CS
A0
A0
Decoder MPU
Port1 Port2 SI SCL P/S GND RES RES VSS
NJU6679
VDD OR GND
RESET
NJU6679
LCD Panel Interface Example
LCD Pan el (128 x 132)
C0
C 63
S0
S 131
C 127
C64
NJU6679
BOTTOM VIEW
CAUTION The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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